lockheedmartin.eightfold.ai
ASIC & FPGA Design Engineer Stf - E4
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Cleared Colorado does not collect applications.
- Clearance
- TS/SCI · obtainable
- Workplace
- Boulder
- Employer posted
- Sep 1, 2026
- First discovered
- Sep 2, 2026 · Found today
- Last source verification
- Sep 2, 2026
- Employer posting
- 996476738230
- Salary
- $135,700 - $251,900
- Work mode
- Onsite
At a glance
ASIC & FPGA Design Engineer Stf - E4 is a TS/SCI · obtainable role from Lockheed Martin with Boulder named as a Colorado workplace. The employer identifies the role as onsite and lists compensation as $135,700 - $251,900. Use the employer posting for the complete responsibilities, qualifications, and application.
Observed listing lifespan
How long similar source listings remain available
Across 1022 observed TS/SCI publication periods, the estimated median source availability is 28 days. This listing has been in its current observed publication period for 0 days and is younger than 100% of those observed periods. This measures employer-source availability, not time-to-hire or time-to-fill.
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